The current evolution of data processing tends towards the grouping of various intelligent devices such as mini-processors and micro-processors into an integrated system wherein several processors and their peripherals are linked by way of common bus lines.
Often the need arises to have messages passed between devices as tasks on different units require parameters, results, buffers, etc. from one another. For example, a task may require access to a file from a mass memory. The device controlling the mass memory is asked by the requesting unit to provide the file. Once the file is retrieved it is sent by the controlling device to the requesting unit. This message passing between devices over a common bus must be controlled in an orderly fashion, since several devices may concurrently require access to the services of other devices. Assignment of priorities and various traffic protocols need to be implemented.
The efficiency of such multi-processor systems with concurrent processing requirements is often limited by the data throughput capability of the bus. The response time of a system is often severely affected by the time devoted by the controlling device to the processing of programmed data transfers over the bus. Such transfers ordinarily require the execution by the controlling device of several instructions for each word of transferred data.
Consequently, under current practices, the connection of additional components to a bussed network, and especially the addition of intelligent units, results in a substantial reduction in the overall system response.
In order to effectively utilize the full bandwidth of a bus system, the participating device should maximize processing without centralized bus traffic management and allow maximum independent concurrent processing and data exchange.
A more efficient bus data transfer would not only allow the interconnection of more units to a common bus, but would also permit the interconnection of two or more independent bus networks through an intelligent unit having access to the various bus systems, without significant effect on the response time of either system.